FIG. 1 schematically illustrates a conventional multiple port system 10 including a plurality of port devices 12. The multiple port system 10 may be used in an application specific integrate circuit (ASIC) design requiring the use of such multiple ports or in a multi-port Application Specific Standard Product (ASSP), for example, in a network interface chip or network interface card. Each port device 12 may be an individual channel core provided in a multiple-channel application of a system-on-chip design. Each of the port devices 12 is identical, and includes its own set of registers (control register set) 14 for configuration and control. Each port device 12 is also referred to as an instance of the identical port, which is instantiated multiple times in a cycle if the system requires.
The control register set 14 is accessible over an industry standard interface and is controlled using control signals having a management frame. For example, if an individual port device needs to be reset, a corresponding bit set is written to the registers in order to initiate a reset operation. Similarly, there are other functions such as “power down” that can be controlled by writing to the respective register bit. This conventional method works fine when the control needs to be done on a “per-port” basis. However, there may be situations where all the ports in the device (ASIC or ASSP) need to be reset simultaneously. There are several ways to achieve such a simultaneous or global control.
One way of implementing a global control is to provide a piece of logic such as an AND gate 16 that monitors the reset signal from each of the ports 12, as shown in FIG. 1. The logic 16 generates a master reset signal when all the reset signals for the ports are active, resetting common logic 18. The drawback of this approach is that a master device (not shown) that provides control signals to the multiple ports needs to write the corresponding register bit in the register set 14 for each port 12. That is, all instances of the port need to be reset to initiate a global reset of the multiple port system 10. This involves a number of write operations to the system 10. Typically, software is used to write the register bits of the individual ports 12, and the software may not be able to complete the write operation to multiple ports within the time period for a single port to come out of reset. The AND logic 16 will work as long as all the ports 12 are in reset at the same time. However, if the first port that was reset completes its reset cycle before the last port is reset, then the AND logic 16 will not be able to perform a global reset. This is a deficiency of the AND logic approach, which becomes more conspicuous as the number of ports increases.
FIG. 2 schematically illustrates a conventional multiple port system 20 employing another approach to the global control. In this approach, a reset signal from one of the ports (port 22a) is considered as an equivalent of a master reset signal, and is used to reset all the ports 22 (and the common logic 28) in case of a system reset. The advantage of this approach is that it does not require monitoring all the individual reset signals from the multiple ports. However, it is impossible to reset the port 22a that is being used as the master reset without placing the entire system into reset. Thus, when the port 22a need to be reset, the entire system 20 must also be reset. Such a reset operation is not desirable.
Accordingly, it would be desirable to provide a system and method that implement global signals in a multiple-port circuit design in a scalable manner.